公司与主要的EDA供应商细密合作，配合开发设计套件，以更好地知足客户种种各样的设计需求。
参考流程
Synopsys
华大九天
Empyrean reference IC design flow
物理验证工具
| Tech. Node | Process | Process Description | CALIBRE | ASSURA | Argus |
|---|---|---|---|---|---|
| 0.11μm | Eflash | P-sub, 1.5V/3.3V/5V | √ | ||
| 0.13μm | Mixed-Signal/RF | P-sub,1.2V/3.3V Including RF | √ | ||
| 0.153μm | MCU | P-sub,5V Including RF | √ | ||
| CMOS | P-sub,7V | √ | |||
| 0.16μm | Logic | P-sub,1.8V/3.3V | √ | ||
| Mixed-Signal/RF | P-sub,1.8V/3.3V, including RF | √ | |||
| 0.18μm | Logic | P-sub, 1.8V/3.3V | √ | ||
| Mixed-Signal/RF | P-sub,1.8V/3.3V, including RF | √ | √ | ||
| HV | P-sub, 1.8V/5V | √ | |||
| 1.8V 18V VGS 18V VDS HVMOS Process | √ | ||||
| MCU | P-sub, 3.3V/5V/6V | √ | √ | ||
| BCD | P-sub, 3.3V/5V | √ | |||
| 25VBCD | P-sub,1.8V&5V VGS 25V VDS Non-EPI BCD | √ | |||
| P-sub,1.8V&5V VGS 25V VDS P-EPI BCD | √ | ||||
| eflash | P-sub,1.8V&3.3V&5V | √ | |||
| SourceDriver | 1.8v&18v | √ | |||
| 3.3v&13.5v | √ | ||||
| 3.3v&18v | √ | ||||
| BCD | 7-30V scalable P-EPI BCD DB | √ | |||
| DB SBCD G2S 7V 80V Process | √ | ||||
| DB SBCD G2S 80V 120V Process | √ | ||||
| DB SBCD G3 Process | √ | ||||
| AB SBCD G1 7V 30V Process | √ | ||||
| AB SBCD G1S Process | √ | ||||
| EEPROM | EEPROM | √ | |||
| 0.25μm | BCD | 5V VGS 25V VDS 2P5M | √ | ||
| 5V VGS 12V/45V VDS 2P5M | √ | ||||
| 30V60V | √ | ||||
| 1P4M Salicide 5V Analog | √ | ||||
| 0.35μm | Flatcell | P-sub,5V SPQM, 0.7μm *0.7μm flatcell cell, single poly, 4 metal | √ | √ | |
| P-sub,3.3V/5V, 0.7μm *0.7μm flatcell, single poly, | √ | √ | |||
| single metal | |||||
| P-sub, 3.5V/5V, 0.63μm *0.63μm flatcell, dual gate oxide | √ | ||||
| Mixed-Signal | P-sub,3.3V/5V | √ | √ | ||
| OTP | Mix OTP DPQM 3.3V 5V | √ | |||
| BCD | 3.3V Vgs 12V_15V Vds | √ | |||
| Logic G2 | 3.3V | √ | |||
| 0.5FEOL/0.35BEOL | Mixed-Signal | 0.5FEOL/0.35BEOL | √ | ||
| 0.5FEOL/0.35BEOL 1.8fF/um^2 | √ | ||||
| Plain-poly, 3~5V | √ | ||||
| 0.5μm | Mixed-Signal | Enhance Analog for 5V | √ | ||
| P-Sub,5V, with PIP/High P2/LVt/Depletion | √ | √ | √ | ||
| P-Sub,5V, with PIP/High P2/LVt/Depletion 1.8FF Cpip | √ | ||||
| HV | P-sub,40V/25V process | √ | √ | ||
| P-sub,Deep Nwell 5V process | √ | √ | |||
| P-sub,5V/18V process | |||||
| BCD | 0.5um 15V(VGS)/15V(VDS) DPTM BCDMOS Process | √ | √ | ||
| 0.5um 5V(VGS)/15V(VDS) DPTM BCDMOS Process | √ | √ | |||
| 0.5um 5V(VGS)/25V(VDS) DPTM BCDMOS Process | √ | √ | |||
| 0.5um 25V(VGS)/25V(VDS) DPTM BCDMOS Process | √ | √ | |||
| 0.5um 5V(VGS)/40V(VDS) DPTM BCDMOS Process | √ | ||||
| 0.5μm FEOL 0.6μm BEOL | |||||
| P-sub,18V/20V thick_ox BCDMOS process | √ | √ | |||
| P-sub,5V/20V thin_Gox BCDMOS process | √ | √ | |||
| P-sub,5V/40V thin_Gox BCDMOS process | √ | √ | |||
| P-sub,25V/40V thick_Gox BCDMOS process | √ | √ | |||
| 0.6μm | Logic | P-sub,5V,plain poly, before N-ROM | √ | ||
| P-sub,LV,plain poly, before N-ROM | √ | ||||
| N-sub,5v,N-ROM before plain poly | √ | ||||
| Mixed- Signal | P-sub, 5V, PIP/High P2 | √ | |||
| P-sub, 5V, PIP/High P2,LVt, Depletion | √ | ||||
| HV | N-sub, 5V-18V | √ | |||
| 1.0μm | MGLV | N-Sub,1.5-5V | √ | ||
| N-Sub,3.0-5V | √ | ||||
| HV | P-sub,5V/40V | √ | |||
| P-sub,5V/40V, 0.5μm backend, and thick Al2 is option | √ | ||||
| P-sub,5V/25V, 0.5μm backend, and thick Al2 is option(HV GOX 600A) | √ | ||||
| 2.0μm | 36V | DN, Nitride Cap, 1M | √ | ||
| DN, Nitride Cap, P-, P+, 1M | √ | ||||
| 18V (5μm Tepi) | DN,SiN Cap, 1M(5μm EPI) | √ |
